Key goals in designing field effect transistors (FETs) for use in high voltage (HV) applications include, but are not limited to, high blocking voltage (BV) (also referred to as high breakdown voltage or high drain-source voltage (VDS)) for operability at high voltages, low ‘ON’ resistance (Ron) for faster switching speeds, lower power losses, relatively small size and enhanced manufacturability in terms of time and cost. Oftentimes, design features that increase the likelihood of meeting one goal (e.g., high BV) result in a decrease in the likelihood of meeting one or more of the other goals (e.g., Ron) such that the design process involves trade-offs.
Recently, planar lateral double-diffused metal oxide semiconductor field effect transistors (LDMOSFETs) have been developed. An LDMOSFET, like a conventional MOSFET, has a channel region that is positioned laterally between a source region and a drain region. However, unlike a conventional MOSFET, the LDMOSFET is asymmetric with the channel region being closer to the source region than the drain region. Specifically, in an LDMOSFET, the channel region is separated from the source region by a first distance and is separated from the drain region by a second distance that is greater than the first distance. The space between the channel region and the drain region includes a relatively low-doped drain drift region that provides ballasting resistance so that the LDMOSFET has a relatively high BV. Additionally, the conductivity level profile of the drain drift region can be graded and, specifically, can increase from the channel region toward the drain region in order to minimize the Ron. While such LDMOSFETs have a relatively high BV and reduced Ron as compared to conventional MOSFETs, further improvements to the LDMOSFET structure and the method of forming the structure are needed in order to further reduce the Ron, to allow for device size scaling and/or to improve manufacturability (i.e., to reduce turn around time and cost associated with manufacturing).